This invention relates to a semiconductor integrated circuit with improved output buffer circuits, resulting in reduced switching noise at output terminals.
Various output buffer circuits can be found in the prior art. The simplest comprises a pair of transistors coupling an output terminal to an upper potential supply line and a lower potential supply line. When the first transistor is switched on and the second is switched off, the output terminal is in the high output state, providing the upper potential to an external load. When the first transistor is switched off and the second is switched on, the output terminal is in the low output state, providing the lower potential to the external load. When both transistors are switched off, the output terminal is in the high-impedance state.
When switched between the high and low output states, this simple output buffer generates a large flow of charge or discharge current on the upper or lower potential supply line, resulting in switching noise. As the speed and current driving ability of output buffers has increased, incorrect circuit operation due to such switching noise has become a major problem.
Japanese Patent Kokai Publication 1087/48806 discloses a prior-art scheme for reducing output buffer switching noise, which is to couple the output terminal to the upper potential supply line through two or more transistors in parallel, and couple the output terminal to the lower potential supply line through two or more transistors in parallel. The switch-on times of these transistors are staggered, thereby reducing noise by restricting charge and discharge current flow.
This prior-art scheme has not proven entirely successful, however. When a large number of output buffers are switched simultaneously from the high to the low output state, for example, they generate a large total discharge current from their loads to the lower potential line. The resulting noise can propagate to other output buffers that are being held in the low output state. Resonance between stray inductance and capacitive loads of the other output buffers may produce an output noise voltage exceeding the peak noise voltage on the lower potential line, disrupting the operation of circuits being driven by those output buffers.